Simple Basic and Convex Processing Time and Power Models for Common Subtractive Manufacturing Processes

by Patterson, Albert E, Peddada, Satya R T and Allison, James T
Reference:
Albert E Patterson, Satya R T Peddada and James T Allison, "Simple Basic and Convex Processing Time and Power Models for Common Subtractive Manufacturing Processes", Engineering System Design Lab: Urbana, IL, USA, Rep. UIUC-ESDL-2019-02.
Bibtex Entry:
@TechReport{Patterson2019TR,
  Title                    = {Simple Basic and Convex Processing Time and Power Models for Common Subtractive Manufacturing Processes},
  Author                   = {Patterson, Albert E and Peddada, Satya R T and Allison, James T},
  Institution              = {Engineering System Design Lab},
  Year                     = {2019},
  Address                  = {Urbana, IL, USA},
  Month                    = dec,
  Number                   = {UIUC-ESDL-2019-02},
  Type                     = {Technical Report},
  Pdf                      = {/publications/Patterson2019TR.pdf},
  Url                      = {http://hdl.handle.net/2142/106014},
  ESDLnote                 = {},
  ESDLid                   = {R8},
}